View MT49H8M32BM-4_3907990.PDF datasheet online --- IC-ON-LINE

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products and specifications discussed herein ar e subject to change by micron without notice. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram features pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_1.fm - rev h 9/06 en 1 ?2001 micron technology, inc. all rights reserved. reduced latency dram (rldram ? ) mt49h8m32 ? 1 meg x 32 x 8 banks mt49h16m16 ? 2 meg x 16 x 8 banks for the latest data sheet, refer to micron?s web site: www.micron.com/products/dram/rldram/ features ? organization: 8 meg x 32, 16 meg x 16 in 8 banks ? cyclic bank addressing for maximum data bandwidth ? non multiplexed addresses ? non interruptible sequential burst of two (2-bit prefetch) and four (4-bit prefetch) ddr ? up to 600 mb/sec/pin data rate ? programmable read latency (rl) of 5-6 ? data valid signal (dvld) activated as read data is available ? data mask signals (dm0/dm1) to mask first and ? second part of write data burst ? ieee 1149.1 compliant jtag boundary scan ? 2.5v vext, 1.8v v dd , 1.8v v dd q i/o ? pseudo-hstl 1.8v i/o supply ? internal auto precharge ? refresh requirements: 32ms at 95c case temperature (8k refresh for each bank, 64k refresh command must be issued in total each 32ms) ? 144-pin, 11mm x 18.5mm bga/fbga package notes: 1. contact factory for availability. options marking ? clock cycle timing 3.3ns (300 mhz) 4ns (250 mhz) 5ns (200 mhz) -33 -4 -5 ?configuration 8 meg x 32 (1 meg x 32 x 8 banks) 16 meg x 16 (2 meg x 16 x 8 banks) mt49h8m32 mt49h16m16 ? operating temperature range commercial:0 to +95c industrial: t c = ?40c to +95c t a = ?40c to 85c none it ?package 144-ball, bga 144-ball, bga (pb-free) 144-ball, fbga 144-ball, fbga (pb-free) fm bm 1 hu ht 1 figure 1: 144-ball fbga general description the micron ? 256mb reduced latency dram (rldram ? ) contains 8 banks x32mb of memory accessible with 32-bit or 16-bit i/os in a double data rate (ddr) form at where the data is provided and syn- chronized with a differential echo clock signal. rldram does not require row/column address multi- plexing and is optimized for fast random access and high-speed bandwidth. rldram is designed for high bandwidth communica- tion data storage?teleco mmunications, networking, and cache applications, etc. table 1: valid part numbers part number description mt49h8m32hu-xx 8 meg x 32 mt49h16m16hu-xx 16 meg x 16
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256m_16_32_rldramtoc.fm - rev h 9/06 en 2 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 functional block diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 ball assignments and descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 mode register set command (mrs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 write basic information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 read basic information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 auto refresh command (aref) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 ieee 1149.1 serial boundary scan (jtag) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 disabling the jtag feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 test access port (tap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 test clock (tck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 test mode select (tms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 test data-in (tdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 test data-out (tdo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 performing a tap reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 tap registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 bypass register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 boundary scan register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 identification (id) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 tap instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 extest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 idcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 sample/preload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 reserved for future use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 recommended dc operation ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256m_16_32_rldramlof.fm - rev h 9/06 en 3 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram list of figures list of figures figure 1: 144-ball fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 figure 2: 8 meg x 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 figure 3: 16 meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 4: clock command/ad dress timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 5: power-up sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 6: clock input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 7: mode register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 8: mode register set timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 9: mode register bit map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 10: write command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 11: basic write burst timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 12: write burst basic sequence: bl = 2; wl = 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 13: write burst basic sequence: bl = 4; wl = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 14: write data mask timing: bl = 2; wl = 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 15: write data mask timing: bl = 4; wl = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 16: write followed by read: bl = 4; rl = 5; wl = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 17: read command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 18: basic read burst timi ng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 19: read burst: bl = 2; rl = 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 20: read burst: bl = 4; rl = 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 21: read followed by write: bl = 2; rl = 5; wl = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 22: read followed by write: bl = 2; rl = 5; wl = 2 ? in terleaved data . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 23: read followed by write: bl = 4; rl = 5; wl = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 24: read followed by write: bl = 4; rl = 5; wl = 1 ? in terleaved data . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 25: auto refresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 26: auto refresh cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 27: tap controller state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 28: tap controller block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 29: tap timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 30: output test conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 31: 144-ball fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 32: 144-ball bga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256m_16_32_rldramlot.fm - rev h 9/06 en 4 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram list of tables list of tables table 1: valid part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: 8 meg x 32 ball assignments (top view) 144-ball fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 table 3: 16 meg x 16 ball assignments (top view) 144-ball fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 table 4: ball descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 5: address widths at different burst lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 table 6: command table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 table 7: description of commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 8: ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 table 9: clock input operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 10: rldram configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 12: timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 13: tap ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 14: tap dc electrical characteristics and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 15: identification register definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 16: scan register sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 17: instruction codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 18: boundary scan (exit) order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 19: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 20: dc electrical characteristics and operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 21: dc electrical characteristics and operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 table 22: capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 table 23: ac electrical characteristics and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 table 24: i dd operating conditions and maximum limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 5 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram functional block diagrams functional block diagrams figure 2: 8 meg x 32 notes: 1. when the bl = 4 setting is used, a18 is a ?don?t care.? a0?a18, b0, b1, b2 c olumn a dd ress buffer c olumn a dd ress c ounter refresh c ounter row de c o d er memory array bank 1 c olumn de c o d er sense amp an d data bus row a dd ress buffer row de c o d er memory array bank 0 c olumn de c o d er sense amp an d data bus row de c o d er memory array bank 2 c olumn de c o d er sense amp an d data bus row de c o d er memory array bank 3 c olumn de c o d er sense amp an d data bus row de c o d er memory array bank 5 c olumn de c o d er sense amp an d data bus row de c o d er memory array bank 4 c olumn de c o d er sense amp an d data bus row de c o d er memory array bank 6 c olumn de c o d er sense amp an d data bus row de c o d er memory array bank 7 c olumn de c o d er c k c ?k# as# we# c s# ref# dm0 dm1 v ref sense amp an d data bus data vali d dvld data rea d stro b e dqs[3:0], dqs#[3:0] input buffers output buffers c ontrol lo g i c an d timin g generator dq0?dq31
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 6 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram functional block diagrams figure 3: 16 meg x 16 notes: 1. when the bl = 4 setting is used, a19 is a ?don?t care.? 2. in the 16 meg x 16 configuration, only dq s [1:0] and dq s #[1:0] are used. a0?a19, b0, b1, b2 c olumn a dd ress buffer c olumn a dd ress c ounter refresh c ounter row de c o d er memory array bank 1 c olumn de c o d er sense amp an d data bus row a dd ress buffer row de c o d er memory array bank 0 c olumn de c o d er sense amp an d data bus row de c o d er memory array bank 2 c olumn de c o d er sense amp an d data bus row de c o d er memory array bank 3 c olumn de c o d er sense amp an d data bus row de c o d er memory array bank 5 c olumn de c o d er sense amp an d data bus row de c o d er memory array bank 4 c olumn de c o d er sense amp an d data bus row de c o d er memory array bank 6 c olumn de c o d er sense amp an d data bus row de c o d er memory array bank 7 c olumn de c o d er c k c k# as# we# c s# ref# dm0 dm1 v ref sense amp an d data bus data vali d dvld data rea d stro b e dqs[1:0], dqs#[1:0] input buffers output buffers c ontrol lo g i c an d timin g generator dq0?dq15
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 7 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram ball assignments and descriptions ball assignments and descriptions notes: 1. no function. this signal is internally connected and has parasiti c characteristics of an address input signal. this may optionally be connected to g nd. notes: 1. no function. this signal is internally connected and has parasi tic characteristics of an i/o sig- nal. this may optionally be connected to g nd. 2. no function. this signal is internally conn ected and has parasitic ch aracteristics of an dq s signal. this may optionally be connected to g nd. table 2: 8 meg x 32 ball assignments (top view) 144-ball fbga 1 2 3 4 5 6 7 8 9 10 11 12 a v ss v ext v ref v ss v ss v ext tm s tck b v ss dq8 dq9 v ss qv ss q dq1 dq0 v ss c v ss dq10 dq11 v dd qv dd q dq3 dq2 v ss d v ss dq s 1dq s 1# v ss qv ss qdq s 0# dq s 0v ss e v ss dq12 dq13 v dd qv dd q dq5 dq4 v ss f dm0 dq14 dq15 v ss qv ss q dq7 dq6 dvld g a5 a6 a7 v dd v dd a2 a1 a0 h a8 a9 v ss v ss v ss v ss a4 a3 j a s # b2 v dd v dd v dd v dd b0 ck k we# ref# v dd v dd v dd v dd b1 ck# l a18 c s #v ss v ss v ss v ss a14 a13 m a15 a16 a17 v dd v dd a12 a11 a10 n dm1 dq22 dq23 v ss qv ss q dq31 dq30 nf 1 p v ss dq20 dq21 v dd qv dd q dq29 dq28 v ss r v ss dq s 2dq s 2# v ss qv ss qdq s 3# dq s 3v ss t v ss dq18 dq19 v dd qv dd q dq27 dq26 v ss u v ss dq16 dq17 v ss qv ss q dq25 dq24 v ss v v ss v ext v ref v ss v ss v ext tdo tdi table 3: 16 meg x 16 ball assignments (top view) 144-ball fbga 1 2 3 4 5 6 7 8 9 10 11 12 a v ss v ext v ref v ss v ss v ext tm s tck b v ss nf 1 nf 1 v ss qv ss q dq1 dq0 v ss c v ss nf 1 nf 1 v dd qv dd q dq3 dq2 v ss d v ss nf 2 nf 2 v ss qv ss qdq s 0# dq s 0v ss e v ss nf 1 nf 1 v dd qv dd q dq5 dq4 v ss f dm0 nf 1 nf 1 v ss qv ss q dq7 dq6 dvld g a5 a6 a7 v dd v dd a2 a1 a0 h a8 a9 v ss v ss v ss v ss a4 a3 j a s #b2v dd v dd v dd v dd b0 ck k we# ref# v dd v dd v dd v dd b1 ck# l a19 c s #v ss v ss v ss v ss a14 a13 m a15 a16 a17 v dd v dd a12 a11 a10 n dm1 nf 1 nf 1 v ss qv ss q dq15 dq14 a18 p v ss nf 1 nf 1 v dd qv dd q dq13 dq12 v ss r v ss nf 1 nf 2 v ss qv ss qdq s 1# dq s 1v ss t v ss nf 1 nf 1 v dd qv dd q dq11 dq10 v ss u v ss nf 1 nf 1 v ss qv ss q dq9 dq8 v ss v v ss v ext v ref v ss v ss v ext tdo tdi
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 8 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram ball assignments and descriptions table 4: ball descriptions symbol type description ck, ck# input input clock: ck and ck# are differential cloc k inputs. addresses and commands are latched on the rising edge of ck, input data is latched on both edges of ck. ck# is ideally 180 degrees out of phase with ck. c s # input chip select: c s # enables the command decoder when low and disables it when hi g h. when the command decoder is disabled, new command s are ignored, but in ternal operations continue. a s #, we#, ref# input command inputs: s ampled at the positive edge of ck, a s #, we#, and ref# define (together with c s #) the command to be executed. a[0:19] input address inputs: a[0:19] define the row and column addresses for read and write operations. during a mode re g i s ter s et (mr s ), the address inputs define the register settings. they are sampled at the rising edge of ck. in the x32 configuration, a[19] is not used. refer to table 5 on page 9 for burst length considerations. ba[0:2] input bank address inputs: s elect to which internal bank a command is being applied. dq[0:31] input/ output data input/output: the dq sign als form the 32-bit data bu s. during read commands, the data is referenced to both edges of dq s /dq s #. during write comma nds, the data is sampled at both edges of ck. dq s x, dq s x# output data read strobes: dq s x and dq s x# are the differential data read strobes. during reads, they are transmitted by the rldram and edge-aligned with data. dq s x# is ideally 180 degrees out of phase with dq s x. dq s 0 and dq s 0# are aligned with dq0?dq7. dq s 1 and dq s 1# are aligned with dq8?dq15. dq s 2 and dq s 2# are aligned with dq16?dq23. dq s 3 and dq s 3# are aligned with dq24?dq31. dvld output data valid: the dvld indicates valid outp ut data. dvld is edge-aligned with dq s x and dq s x#. dm0, dm1 input input data mask: dm0 and dm1 are the input mask signal for write data. the first half of the input data burst is mas ked when dm0 is sampled hi g h along with the write command. the second half of the input data burst is masked when dm1 is sampled hi g h along with the write command. tm s tdi input ieee 1149.1 test inputs: je dec-standard 1.8v i/o levels. these balls may be left as no connect if the jta g function is not us ed in the circuit. tck input ieee 1149.1 clock input: jedec- standard 1.8v i/o levels. this ball must be tied to v ss if the jta g function is not used in the circuit. tdo output ieee 1149.1 test output: jedec-standard 1.8v i/o level. v ref input input reference voltage: nominally v dd q/2. provides a referenc e voltage for the input buffers. v ext s upply power supply: 2.5v nominal. s ee table 20 on page 35 for range. v dd s upply power supply: 1.8v nominal. s ee table 20 on page 35 for range. v dd q s upply power supply: isolated output buffer supply. nominally, 1.8v. s ee table 20 on page 35 for range. v ss s upply power supply: g nd. v ss q s upply power supply: isolated output buffer supply. g nd. nf ? no function: these balls may be connected to ground.
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 9 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram commands commands according to the functional signal description, the following command sequences are possible. all input states or sequences not shown are illegal or reserved. all command and address inputs must meet setup and ho ld times around the rising edge of ck. notes: 1. x = ?don?t care? h = logic hi g h l = logic low a = valid address ba = valid bank address 2. in the x32 configuration a19 is not used. 3. s ee above table; address widths at different burst lengths. 4. only a(17:0) are used for the mr s command. table 5: address widths at different burst lengths burst length x32 x16 bl = 2 18:0 19:0 bl = 4 17:0 18:0 ta bl e 6 : com ma nd tab le note 1 operation cs# as# we# ref# a[19:0] 2, 3 b[2:0] dm[1:0] read cycle l l h h valid valid x write cycle l l l h valid valid valid nop: no operation lhhh x x x de s elect hxxx x x x auto refre s h lhhl xvalidx mr s : mode re g i s ter s et 4 l l l l valid x x
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 10 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram commands notes: 1. when the chip is deselected, internal nop commands are generated and no commands are accepted. 2. actual refresh is 32ms/8k/8 = 0.488s. 3. actual refresh is 32ms/8k = 3.90s. table 7: description of commands command description de s el/nop 1 the nop command is used to perform a no operation to the rldram, which es sentially deselects the chip. use the nop command to pr event unwanted commands from be ing registered during idle or wait states. operations already in progress are not affected. output values depend on command history. mr s the mode register is set via the address inputs a(17:0). s ee figure 9 on page 15 for further information. the mr s command can only be issued when al l banks are idle and no bursts are in progress. read the read command is used to initiate a burst read access to a bank. the value on the ba(2:0) inputs selects the bank, and the address provided on inpu ts a(19:0) selects the data location within the bank. write the write command is used to initiate a burst write access to a bank. the value on the ba(2:0) inputs selects the bank, and the ad dress provided on inputs a(19:0) se lects the data location within the bank. input data appearing on the dqs is writ ten to the memory array subject to the dmx input logic level appearing coincident with the write command. if the dm 0 signal is registered low, the first half of the burst write data will be written to memory, if registered hi g h, the corresponding data inputs will be ignored (i.e., this part of the data word will not be writte n). if the dm1 signal is registered low, the second half of the burst wri te data will be written to memory, if registered hi g h, the corresponding data inputs will be ignored (i.e., this part of the data word will not be written). aref the aref is used duri ng normal operation of the rldram to refresh the memory content of a bank. the command is nonpersistent, so it must be issued each time a refr esh is required. the value on the ba(2:0) inputs selects the bank. the refresh address is generated by an inte rnal refresh controller, effectively making each addre ss bit a ?don?t care? during th e aref command. the rldram requires 64k cycles at an aver age periodic interval of 0.49s 2 (max). to improve efficiency, eight aref commands (one for eac h bank) can be posted to the rldram at periodic intervals of 3.9s. 3
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 11 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram commands notes: 1. all timing parameters are measured relative to the crossing point of ck/ck# and to the crossing point with v ref of the command and address signals. 2. ck/ck# input slew rate must be >1v/ns (>2v/ns if measured differentially). 3. the signal input slew rate must be >1v/ns. 4. parameter only valid within one dq s /dq group, e.g., dq s 0, dq s 0#, and dq0?dq7; dq s 1, dq s 1#, and dq8?dq15. 5. the rising and falling edges of dvld are referenced to falling edges of dq s . figure 4: clock command/address timings table 8: ac electrical characteristics note 1 description symbol -33 -4 -5 units notes min max min max min max clock clock cycle time t ck 3.3 4.0 5.0 ns 2 s ystem frequency f ck 300 250 200 mhz clock hi g h time t ckh 0.45 0.55 0.45 0.55 0.45 0.55 t ck clock low time t ckl 0.45 0.55 0.45 0.55 0.45 0.55 t ck mode re g i s ter s et cycle time to any command t mr s c444 t ck setup times 3 address/command and input setup time t a s / t c s 1.0 1.0 1.0 ns data-in and data mask to dk setup time t d s 0.5 0.5 0.5 ns hold times address/command and input hold time t ah/ t ch 1.0 1.0 1.0 ns data-in and data mask to dk hold time t dh 0.5 0.5 0.5 ns data and data strobe dq s , dq s # hi g h time t dq s h 0.4 0.6 0.4 0.6 0.4 0.6 t ck dq s , dq s # low time t dq s l 0.4 0.6 0.4 0.6 0.4 0.6 t ck clock to dq s , dq s # t ckdq s 2.4 3.9 2.4 3.9 2.4 3.9 ns dq s to output valid t dq s q 0.35 0.35 0.35 ns 4 dq s to output high-z t q s qhz 0.4 0.4 0.4 ns dq s to dvld t q s vld ?0.4 0.4 ?0.4 0.4 ?0.4 0.4 ns 5 ck# ck t ckh t ckl t ah, t ch t a s , t c s t ck cmd, addr don?t care valid valid valid
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 12 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram initialization initialization the rldram must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined operations or permanent damage to the device. the following sequence is used for power-up: 1. apply power (v ext , v dd , v dd q, v ref ) and start clock as soon as the supply voltages are stable. apply v dd and v ext before or at the same time as v dd q. apply v dd q before or at the same time as v ref . although there is no timing relation between v ext and v dd , the chip starts the power-up sequence only after both voltages are at their nominal levels. the pad supply must not be applied before the core supplies. ck/ck# must meet v id ( dc ) prior to being applied. maintain all remaining balls in nop condi- tions. 2. maintain stable conditions for 200s (min). 3. issue three mode register set (mrs) commands: two dummies plus one valid mrs. it is recommended that the dummy mrs commands are the same value as the desired mrs. 4. t mrsc after the valid mrs, issue eight au to refresh commands, one on each bank and separated by 2,048 cycles. initial bank refresh order does not matter. 5. after t rc, the chip is ready for normal operation. figure 5: power-up sequence notes: 1. mr s : mr s command rfx: refre s h bank x ac: any command 2. during t mr s c, nop command must be given on the rising edge of ck. 3. when the rldram is powered up with the matched impedance mode inactive, the 2,048 cycles between the eight refre s h commands are not required. these cycles are necessary in order to calibrate the output drivers. v ext v dd v dd q v ref c k# c k c md 200s min t mrs c 2 t r c 2,048 c y c les min 3 6 2,048 c y c les min 3 mrs mrs mrs rf0 rf1 rf7 a c don?t c are add nop nop nop
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 13 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram initialization figure 6: clock input notes: 1. dq s x and dq s x# have the same requirements as ck and ck#. 2. all voltages referenced to v ss . 3. tests for ac timing, i dd , and electrical ac and dc characteristics may be conducted at nom- inal reference/supply voltage le vels, but the related specifications and device operations are tested for the full vo ltage range specified. 4. outputs (except for i dd measurements) measured with equivalent load. 5. ac timing and i dd tests may use a v il -to-v ih swing of up to 1.5v in the test environment, but input timing is st ill referenced to v ref (or to the crossing poin t for ck/ck#), and param- eter specifications are tested fo r the specified ac input levels under normal use conditions. the minimum slew rate for the input si gnals used to test the device is 1v/ns in the range between v il ( ac ) and v ih ( ac ). 6. the ac and dc input level specif ications are as defined in the h s tl s tandard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as the signal does not ring back above [below] the dc input low [hi g h] level). 7. the ck/ck# input reference level (for timing re ferenced to ck/ck#) is the point at which ck and ck# cross. the input reference level for signals other than ck/ck# is v ref . 8. ck and ck# input slew rate must be 1v/ns ( 2v/ns if measured differentially). 9. v id is the magnitude of the difference between the input level on ck and the input level on ck#. 10. the value of v ix is expected to equal v dd q/2 of the transmitting device and must track vari- ations in the dc level of the same. 11. ck and ck# must cros s within this region. 12. ck and ck# must meet at least v id ( dc ) min when static and centered around v dd q/2. 13. minimum peak-to-peak swing. table 9: clock input operating conditions notes 1?8 parameter/condition symbol min max units notes clock input voltage level; ck and ck# v in ( dc )?0.3v dd q + 0.3 v clock input differential voltage; ck and ck# v id ( dc )0.3v dd q + 0.6 v 9 clock input differential voltage; ck and ck# v id ( ac )0.6v dd q + 0.6 v 9 clock input crossing point voltage; ck and ck# v ix ( ac )v dd q/2 - 0.15 v dd q/2 + 0.15 v 10 ck ck# v in ( dc ) max 11 12 maximum clock level minimum clock level 13 v in ( dc ) min v dd q/2 v dd q/2 + 0.15 v dd q/2 - 0.15 x v ix ( ac ) min x v id ( dc ) v ix ( ac ) max v id ( ac )
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 14 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram mode register set command (mrs) mode register set command (mrs) the mode register stores the data for contro lling the operating modes of the memory. it programs the rldram configuration, burst length, and i/o options. during a mode register set command, the address inputs a(17:0) are sampled and stored in the mode register. t mrsc must be met before any command can be issued to the rldram. the mode register may be set at any time during device operation. however, any pending operations are not guaranteed to successfully complete. figure 7: mode register set notes: 1. cod: code to be loaded into the register figure 8: mode register set timing notes: 1. mr s : mr s command ac: any command c k# c k we# ref# a(17:0) c s# c od a(19:18) ba(2:0) don ? t c are as# c k# c k c md t mrs c mrs nop nop a c don ? t c are
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 15 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram mode register set command (mrs) figure 9: mode register bit map notes: 1. bits a(17:6) must be set to zero. 2. h s tl-compliant current specification. 3. automatic i/o impedance calibratio n is activated in matched mode. a2 a3 a(17: 6 ) a1 a0 a4 a5 a3 0 1 burst len g th 4 reserve d 1 a4 0 1 a2 a1 a0 10 c onfi g uration rldram c onfi g uration 3 2 ( d efault) reserve d reserve d reserve d 1 2 2 ( d efault) a c tive 3 mat c he d mo d e driver stren g th burst len g th ina c tive ( d efault) 2 3 4 10 11 01 01 00 00 1 1 0 0 1 0 1 0 11 mat c he d mo d e 0 1 reserve d 8ma ( d efault) a5 driver stren g th 2
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 16 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram configuration table configuration table the table below shows the different rldram configurations that can be programmed into the mode register for different operat ing frequencies. the read and write latency ( t rl and t wl) values, along with the row cycle times ( t rc), are shown in clock cycles, as well as in nanoseconds. the shaded areas correspond to configurations that are not allowed. write basic information write accesses are initiated with a write command, as shown in the figure 10. row and bank addresses are provided together with the write command. during write commands, data will be register ed at both edges of ck according to the programmed burst length (bl). th e first valid data will be registered with the first rising ck edge wl cycles after the write command has been issued. any write burst may be followed by a su bsequent read command. figure 16 on page 20 illustrates the timing requirements for a write followed by a read for burst of four. setup and hold times for incoming dq relative to the ck edges are specified as t ds and t dh. the first or second part of the incoming data burst is masked if the corresponding dmx signal is sampled high along with the wr ite command. the setup and hold times for data mask are the same as for address and command. table 10: rldram configuration table frequency symbol configuration units 1 2 3 4 t rc 5678cycles t rl 5 5 5 6 cycles t wl (bl = 2) 2 2 2 3 cycles t wl (bl = 4) 1 1 1 2 cycles 300 mhz t rc 26.7 ns t rl 20.0 ns t wl (bl = 2) 10.0 ns t wl (bl = 4) 6.7 ns 250 mhz t rc 28.0 32.0 ns t rl 20.0 24.0 ns t wl (bl = 2) 8.0 12.0 ns t wl (bl = 4) 4.0 8.0 ns 200 mhz t rc 25.0 30.0 35.0 40.0 ns t rl 25.0 25.0 25.0 30.0 ns t wl (bl = 2) 10.0 10.0 10.0 15.0 ns t wl (bl = 4) 5.0 5.0 5.0 10.0 ns
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 17 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram write basic information figure 10: write command notes: 1. a: address ba: bank address dm: data mask figure 11: basic write burst timing table 11: timing parameters symbol -33 -4 -5 units min/max min/max min/max t d s 0.5 0.5 0.5 ns t dh 0.5 0.5 0.5 ns we# ref# c s# a ba a(20:0) ba(2:0) don ? t c are as# dm dm(1:0) dq d0 d1 d2 d3 c k# c k t dh t ds t dh t ds don ? t c are write laten c y
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 18 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram write basic information figure 12: write burst basic sequence: bl = 2; wl = 3 figure 13: write burst basic sequence: bl = 4; wl = 2 notes: 1. a/ba x : address a of bank x wr: write d xy : data y to bank x wl: write latency 2. any free bank may be used in any given cmd. the sequence shown is only one example of a bank sequence. c k# c k c md 012345 6 78 addr dq d2a d3a d2 b d3 b d4a d4 b d5a d5 wr a ba0 a ba1 a ba2 a ba3 a ba4 a ba5 a ba 6 a ba7 a ba0 wr wr wr wr wr wr wr wr don ? t c are d0a d1a d0 b d1 b wl = 3 c k# c k c md 012345 6 78 addr dq d1a d1 c d1 b d1 d d2a d2 b d2 c d3 wr a ba0 a ba1 a ba2 a ba3 a ba0 nop wr nop wr nop wr nop wr don ? t c are d0a d0 c d0 b d0 d wl = 2 d2 d d3a
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 19 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram write basic information figure 14: write data mask timing: bl = 2; wl = 2 notes: 1. a/ba x : address a of bank x wr: write d xy : data y to bank x wl: write latency 2. any free bank may be used in any given cmd. the sequence shown is only one example of a bank sequence. c k# c k c md 012345 6 78 addr dq d3a d4a d3 b d4 b d5a d5 b d 6 a d 6 wr a ba0 a ba1 a ba2 a ba3 a ba4 a ba5 a ba 6 a ba7 a ba0 wr wr wr wr wr wr wr wr don ? t c are d1a d2a d1 b d2 b wl = 2 dm0 dm1 d0a d0 b data maske d
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 20 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram write basic information figure 15: write data mask timing: bl = 4; wl = 1 figure 16: write followed by read: bl = 4; rl = 5; wl = 1 notes: 1. a/ba x : address a of bank x wr: write d xy : data y to bank x wl: write latency rd: read q xy : data y from bank x rl: read latency ck# ck cmd 012 34 567 8 addr dq d2c d4a d2d d4b d4c d4d d6c d6 wr a ba0 a ba2 a ba4 a ba6 a ba0 nop wr nop wr nop wr nop wr d0c d2a d0d d2b wl = 1 dm0 dm1 d0a d0b data masked d6a d6b don?t care undefined ck# ck cmd 012 34567 89 addr wl = 1 rl = 5 dq q1a q1c q1b q1d q2a d0a d0b d0c d0d wr a ba0 a ba1 a ba2 rd wr rd nop nop nop nop nop nop dq s x dq s x# don?t care q1d q2a a ba3 d3a d3b d3c d3d
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 21 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram read basic information read basic information read accesses are initiated with a read command, as shown in figure 17. row and bank addresses are provided with the read command. during read bursts, the memory device drives the read data edge-aligned with the dqs signal. after a programmable re ad latency, data is available at the outputs. the data valid signal indicates that valid data will be present in the next half clock cycle. the skew between dqs and the crossing point of ck is specified as t ckdqs. t dqsq is the skew between dqs and the last valid data edge considered over all the data gener- ated at the dq signals. t dqsq is derived at each dqs clock edge and is not cumulative over time. after completion of a burst, assuming no other commands have been initiated, output data (dq) will go to high-z. back-to-back read commands are possible, producing a continuous flow of output data. the data valid window is derived from each dqs transition and is defined as: min ( t ckh, t ckl) - 2 t dqsq(max) any read burst may be followed by a subsequent write command. figures 21?24 on page 24?25 illustrate the timing requirem ents for a read followed by a write. depending on the programmed read latency, a read-to-write delay occurs in order to prevent bus contention. some systems having long line lengths or severe skews may need additional idle cycles inserted. figure 17: read command notes: 1. a: address ba: bank address c k# c k we# ref# c s# a ba a(20:0) ba(2:0) don ? t c are as#
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 22 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram read basic information figure 18: basic read burst timing notes: 1. minimum data valid window can be expressed as min ( t ckh, t ckl) - 2 t dq s q (max). table 12: timing parameters symbol -33 -4 -5 units min max min max min max t ck 3.3 4.0 5.0 ns t ckh 0.45 0.55 0.45 0.55 0.45 0.55 t ck t ckl 0.45 0.55 0.45 0.55 0.45 0.55 t ck t ckdq s 2.4 3.9 2.4 3.9 2.4 3.9 ns t dq s q 0.35 0.35 0.35 ns t q s qhz 0.4 0.4 0.4 ns t q s vld ?0.4 0.4 ?0.4 0.4 ?0.4 0.4 ns t dq s h 0.4 0.6 0.4 0.6 0.4 0.6 t ck t dq s l 0.4 0.6 0.4 0.6 0.4 0.6 t ck undefined t qsvld t qsvld t dqsq note 1 t dqsq t qsqhz t c kdqs dvld dq c k# c k dqsx dqs# t c kh t c kl t c k q0 q1 q2 q3 t dqsl t dqsh
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 23 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram read basic information figure 19: read burst: bl = 2; rl = 5 figure 20: read burst: bl = 4; rl = 5 notes: 1. a/ba x : address a of bank x d xy : data y to bank x rc: row cycle time rl: read latency c k# c k c md 012345 6 78 addr rl = 5 dq dqsx dqsx# q0a q1a q0 b q1 b q2a q2 b q3a rd a ba0 a ba1 a ba2 a ba3 a ba4 a ba7 a ba 6 a ba5 a ba0 rd rd rd rd rd rd rd rd don ? t c are undefined dvld c k# c k c md 012345 6 78 addr rl = 5 dq dqsx dqsx# q0a q0 c q0 b q0 d q2a q2 b q2 c rd a ba0 a ba2 a ba4 a ba 6 a ba1 nop rd nop rd nop rd nop rd don ? t c are undefined dvld
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 24 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram read basic information figure 21: read followed by write: bl = 2; rl = 5; wl = 2 figure 22: read followed by write: bl = 2; rl = 5; wl = 2 ? interleaved data notes: 1. a/ba x : address a of bank x d xy : data y to bank x rd: read rl: read latency wl: write latency c k# c k c md 012345 6 78 addr rl = 5 dqsx dqsx# rd a ba0 a ba1 nop nop nop nop wr wr nop nop don ? t c are undefined 9 a ba2 wl = 2 dvld nop dq q0a q0 b d1a d1 b d2a d2 b c k# c k c md 012345 6 78 addr rl = 5 dq dqsx dqsx# rd a ba0 a ba1 wr nop nop nop wr nop nop nop don ? t c are undefined 9 a ba2 wl = 2 dvld wl = 2 nop q0a q0 b d2a d2 b d1a d1 b
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 25 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram read basic information figure 23: read followed by write: bl = 4; rl = 5; wl = 1 figure 24: read followed by write: bl = 4; rl = 5; wl = 1 ? interleaved data notes: 1. a/ba x : address a of bank x d xy : data y to bank x rd: read rl: read latency wl: write latency c k# c k c md 012345 6 78 addr rl = 5 dq dqsx dqsx# rd a ba0 a ba1 nop nop nop nop nop nop nop don ? t c are undefined 9 wl = 1 dvld wr nop q0a q0 b d1a d1 b d1 c d1 q0 c q0 d c k# c k c md 012345 6 78 addr rl = 5 dq dqsx dqsx# q0a q0 b d2a d2 b rd a ba0 a ba2 wr nop nop nop nop nop nop don ? t c are undefined 9 wl = 1 d2 c dvld wr nop d2 q0 c q0 d d1a d1 b d1a d1 b a ba1 wl = 1
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 26 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram auto refresh command (aref) auto refresh command (aref) aref is used to perform a refresh cycle on 1 row in a specific bank. the row addresses are generated by an internal refresh counter for each bank; external address balls are ?don?t care.? the delay between the aref command and a subsequent command to the same bank must be at least t rc. within a period of 32ms ( t ref), the entire memory must be refreshed. figure 25 illus- trates an example of a continuous refresh sequence. other refresh strategies, such as burst refresh, are also possible. figure 25: auto refresh command notes: 1. ba: bank address figure 26: auto refresh cycle notes: 1. acx: any command on bank x arfx: auto refresh bank x acy: any command on different bank 2. t rc is configuration-dependent. refer to table 10 on page 16. c k# c k we# ref# c s# ba a(20:0) ba(2:0) don ? t c are as# c k# c k c md t r c arf x a c y a c x a c y arf x a c y don ? t c are
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 27 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram ieee 1149.1 serial boundary scan (jtag) ieee 1149.1 serial boundary scan (jtag) the rldram incorporates a serial boundary scan test access port (tap). this port oper- ates in accordance with ieee standard 1149 .1-1990 but does not have the set of func- tions required for full 1149.1 compliance. th ese functions from the ieee specification are excluded because their inclusion places an added delay in the critical speed path of the rldram. note that the tap controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant taps. the tap operates using jedec-standard 1.8v i/o logic levels. the rldram contains a tap controller, inst ruction register, boundary scan register, bypass register, and id register. disabling the jtag feature it is possible to operate the rldram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be unconne cted. they may alternately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this ball unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi ball is used to serially input inform ation into the registers and can be connected to the input of any of the registers. the re gister between tdi and tdo is chosen by the instruction that is loaded into the tap inst ruction register. for information on loading the instruction register, see figure 27 on page 28. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most signif- icant bit (msb) of any register. (see figure 28 on page 29.)
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 28 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram test access port (tap) figure 27: tap controller state diagram notes: 1. the 0/1 next to each sta te represents the value of tm s at the rising edge of t ck. test data-out (tdo) the tdo output ball is used to serially cloc k data-out from the registers. the output is active depending upon the current state of the tap state machine. (see figure 27.) the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. (see figure 28 on page 29.) performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of th e rldram and may be performed while the rldram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo balls and allow data to be scanned into and out of the rldram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls, as shown in figure 28. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board-level serial test data path. test-logi c reset run-test/ idle sele c t dr-s c an sele c t ir-s c an c apture-dr shift-dr c apture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 29 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram test access port (tap) bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the rldram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the rldram. several no connect (nc) balls are also included in the scan register to reserve pins. the rldram has a 104-bit register. the boundary scan register is loaded with the contents of the ram i/o ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr state. the extest, sample/ preload, and sample z instructions can be used to capture the contents of the i/o ring. the boundary scan order tables (see page 34) show the order in which the bits are connected. each bit corresponds to one of the balls on the rldram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. figure 28: tap controller block diagram notes: 1. x = 103 for all configurations identification (id) register the id register is loaded with a vendor-speci fic, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register. the idcode is hard- wired into the rldram and can be shifted out when the tap controller is in the shift- dr state. the id register has a vendor code and other information described in table 15 on page 33. bypass re g ister 0 instru c tion re g ister 0 1 2 i d entifi c ation re g ister 0 1 2 29 30 31 . . . boun d ary s c an re g ister 0 1 2 . . x . . . sele c tion c ir c uitry sele c tion c ir c uitry t c k tms tap c ontroller tdi tdo
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 30 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram tap instruction set tap instruction set overview eight different instructions are possible wi th the three-bit instruction register. all combinations are listed in the instructio n codes table (see page 33). three of these instructions are listed as reserved and should not be used. the other five instructions are described in detail below. the tap controller used in this rldram is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instruct ions are not fully implemented. the tap controller cannot be used to load address, data or control signals into the rldram and cannot preload the i/o buffers. the rldram does not implement the 1149.1 commands extest or intest or the preloa d portion of sample/preload; rather it performs a capture of the i/o ring when these instructions are executed. instructions are loaded into the tap contro ller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register thro ugh the tdi and tdo balls. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be executed whenever the instruc- tion register is loaded with all zeros. extest is not implemented in the tap controller, hence this device is not ieee 1149.1 compliant. the tap controller does recognize an all-0 in struction. when an ex test instruction is loaded into the instruction register, the rldram responds as if a sample/preload instruction has been loaded. extest does not place the rldram outputs in a high-z state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the in struction register between the tdi and tdo balls and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the in struction register upon power-up or when- ever the tap controller is given a test logic reset state. sample/preload sample/preload is a 1149.1 mandatory instruction. the preload portion of this instruction is not implemented, so the device tap controller is not fully 1149.1- compliant. when the sample/preload instruction is load ed into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and bidirec- tional balls is captured in the boundary scan register. the user must be aware that the tap controll er clock can only operate at a frequency up to 50 mhz, while the rldram clock operates significantly faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 31 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram tap instruction set input or output will undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guarantee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the rldram signal must be stabilized long enough to meet the tap controller?s capture setup plus hold time ( t cs plus t ch). the rldram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/ preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck# captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo balls. note that since the preload part of the command is not implemented, putting the tap to the update-dr state while performing a sample/preload instruction will have the same effect as the pause-dr command. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift-dr state, the bypass register is placed between tdi and tdo. the advantage of the bypass instruction is that it shortens th e boundary scan path when multiple devices are connected together on a board. reserved for future use the remaining 22 instructions are not implemented but are reserved for future use. do not use these instructions. figure 29: tap timing t tlth test c lo c k (t c k) 12345 6 test mo d e sele c t (tms) t thtl test data-out (tdo) t thth test data-in (tdi) t thmx t mvth t thdx t dvth t tlox t tlov don ? t c are undefined
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 32 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram tap instruction set notes: 1. t c s and t ch refer to the setup and hold time requ irements of latching data from the bound- ary scan register table 13: tap ac electrical characteristics note 1; +0c t c +95c; +1.7v v dd +1.95v description symbol min max units clock clock cycle time t thth 20 ns clock frequency f tf 50 mhz clock hi g h time t thtl 10 ns clock low time t tlth 10 ns output times tck low to tdo unknown t tlox 0 ns tck low to tdo valid t tlov 10 ns tdi valid to tck hi g h t dvth 5 ns tck hi g h to tdi invalid t thdx 5 ns setup times tm s setup t mvth 5 ns capture setup t c s 5ns hold times tm s hold t thmx 5 ns capture hold t ch 5 ns
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 33 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram tap instruction set notes: 1. all voltages referenced to v ss ( g nd). 2. overshoot: v ih ( ac ) v dd + 0.7v for t t ck/2. undershoot: v il ( ac ) ?0.5v for t t ck/2. during normal operation, v dd q must not exceed v dd . table 14: tap dc electrical characteristics and operating conditions +0c t c 95c; +1.7v v dd +1.95v, unless otherwise noted description conditions symbol min max units notes input high (logic 1) voltage v ih v ref + 0.15 v dd + 0.3 v 1, 2 input low (logic 0) voltage v il v ss q - 0.3 v ref - 0.15 v 1, 2 input leakage current 0v v in v dd il i ?5.0 5.0 a output leakage current output disabled, 0v v in v dd il o ?5.0 5.0 a output low voltage i olc = 100a v ol 10.2v1 output low voltage i olt = 2ma v ol 20.4v1 output high voltage |i ohc | = 100a v oh 1v dd q - 0.2 v 1 output high voltage |i oht | = 2ma v oh 2v dd q - 0.4 v 1 table 15: identification register definitions instruction field all devices description revi s ion number (31:28) 00ab ab = 10 for x3 2, 01 for x16 device id (27:12) micron jedec id code (11:1) 0000000010100111 00000101100 this represents the part number allows unique identification of rldram vendor id register presence indicator (0) 1 indicates the presence of an id register table 16: scan register sizes register name bit size instruction 8 bypass 1 id 32 boundary s can 104 table 17: instruction codes instruction code description exte s t 0000 0000 captures i/o ring contents. places the boundary scan register between tdi and tdo. this instruction is not 1149.1-compliant. th is operation does not affect rldram operations. s ample/preload 0000 0101 captures i/o ring contents. places the boundary scan register between tdi and tdo. this instru ction does not implement 11 49.1 preload function and is therefore not 1149.1-compliant. idcode 0010 0001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect rldram operations. bypa ss 1111 1111 places the bypass register between tdi and tdo. this operation does not affect rldram operations.
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 34 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram tap instruction set notes: 1. any unused pins that are in the order will read as a logic ?0.? table 18: boundary scan (exit) order note 1 bit# fbga ball bit# fbga ball bit# fbga ball 1 k1 36 r11 71 c11 2 k2 37 p11 72 c11 3 l2 38 p11 73 c10 4 l1 39 p10 74 c10 5 m1 40 p10 75 b11 6m341n1176b11 7m242n1177b10 8n143n1078b10 9n344n1079b3 10 n3 45 n12 80 b3 11 n2 46 m11 81 b2 12 n2 47 m10 82 b2 13 p3 48 m12 83 c3 14 p3 49 l12 84 c3 15 p2 50 l11 85 c2 16 p2 51 k11 86 c2 17 r2 52 k12 87 d3 18 r3 53 j12 88 d2 19 t2 54 j11 89 e2 20 t2 55 h11 90 e2 21 t3 56 h12 91 e3 22 t3 57 g 12 92 e3 23 u2 58 g 10 93 f2 24 u2 59 g 11 94 f2 25 u3 60 f12 95 f3 26 u3 61 f10 96 f3 27 u10 62 f10 97 f1 28 u10 63 f11 98 g 2 29 u11 64 f11 99 g 3 30 u11 65 e10 100 g 1 31 t10 66 e10 101 h1 32 t10 67 e11 102 h2 33 t11 68 e11 103 j2 34 t11 69 d11 104 j1 35 r10 70 d10
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 35 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram electrical characteristics electrical characteristics stresses greater than those listed in table 19 may cause permanent damage to the device. this is a stress rating only, and functi onal operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to abso lute maximum rating conditio ns for extended periods may affect reliability. notes: 1. s upply relative to v ss 2. junction temperature depends upon package type, cycle time, load ing, ambient tempera- ture, and airflow. recommended dc operation ranges all values are recommended operating conditio ns unless otherwise noted. external on board (pcb) capacitance values are required as follows: ?v dd q: 2 0.1f/device ?v dd : 2 0.1f/device ?v ref : 0.1f/device ?v ext : 0.1f/device notes: 1. all voltages referenced to v ss ( g nd). 2. during normal operation, v dd q must not exceed v dd . 3. typically the value of v ref is expected to be 0.5x v dd q of the transmitting device. v ref is expected to track variations in v dd q. 4. peak-to-peak ac noise on v ref must not exceed 2% v ref ( dc ). table 19: absolute maximum ratings parameter min max units notes s torage temperature ?55 +150 c i/o voltage ?0.3v v dd q + 0.3 v voltage on v ext ?0.3 +2.8 v 1 voltage on v dd ?0.3 +2.1 v 1 voltage on v dd q ?0.3 +2.1 v 1 junction temperature 110 c 2 table 20: dc electrical characteristics and operating conditions 0c t c +95c; +1.7v v dd +1.95v unless otherwise noted descriptions symbol min max units notes s upply voltage v ext 2.38 2.63 v 1 s upply voltage v dd 1.7 1.95 v 1 isolated output buffer supply v dd q1.7v dd v1, 2 reference voltage v ref 0.49 v dd q 0.51 v dd q v 1, 3, 4
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 36 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram electrical characteristics notes: 1. all voltages referenced to v ss ( g nd). 2. overshoot: v ih ( ac ) v dd + 0.7v for t t ck/2 undershoot: v il ( ac ) ? 0.5v for t t ck/2 during normal operation, v dd q must not exceed v dd . control input signals may not have pulse widths less than t ck/2 or operate at frequencies exceeding t ck (max). 3. ac load current is higher than the shown dc values. ac i/o curv es are available upon request. 4. h s tl outputs meet jedec h s tl class i and class ii standards. figure 30: output test conditions table 21: dc electrical characteristics and operating conditions 0c t c +95c; +1.7v v dd +1.95v unless otherwise noted description conditions symbol min max units notes input high (logic 1) voltage input low (logic 0) voltage output high voltage output low voltage matched impedance mode v ih v ref + 0.15 v dd q + 0.3 v 1, 2 matched impedance mode v il v ss q - 0.3 v ref - 0.15 v 1, 2 matched impedance mode v oh v dd qv1, 3, 4 matched impedance mode v ol 0v1, 3, 4 input high (logic 1) voltage input low (logic 0) voltage output high voltage output low voltage h s tl strong v ih v ref + 0.1 v dd q + 0.3 v 1, 2 h s tl strong v il v ss q - 0.3 v ref - 0.1 v 1, 2 h s tl strong v oh v dd q - 0.4 v 1, 3, 4 h s tl strong v ol 0.4 v 1, 3, 4 clock input leakage current i lc ?5 5 a input leakage current 0v v in v dd qi li ?5 5 a output leakage current i lo ?5 5 a reference voltage current i ref ?5 5 a table 22: capacitance description conditions symbol min max units address/control input capacitance t a = 25 c; f = 1 mhz c i 2.0 4.0 pf input/output capacitance (dq) c o 2.0 4.0 pf clock capacitance c ck 2.0 4.0 pf table 23: ac electrical characteristics and operating conditions 0c t c +95c; +1.7v v dd +1.95v unless otherwise noted description conditions symbol min max units input high (logic 1) voltage input low (logic 0) voltage matched impedance mode v ih v ref + 0.3 v dd q + 0.3 v matched impedance mode v il v ss q - 0.3 v ref - 0.3 v input high (logic 1) voltage input low (logic 0) voltage h s tl strong v ih v ref + 0.2 v dd q + 0.3 v h s tl strong v il v ss q - 0.3 v ref - 0.2 v 10 pf dq 50 ohm v dd q/2 test point
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 37 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram electrical characteristics notes: 1. i dd specifications are tested after the de vice is properly initialized. +0c tc +95c; +1.7v v dd +1.95v + 1.4v v dd q v dd . 2. t ck = t dk = min, t rc = min. 3. input slew rate is specified in table 21, ?d c electrical characteristics and operating condi- tions,? on page 36. 4. definitions for i dd conditions: 4a. low is defined as v in v il (ac) max. 4b. hi g h is defined as v in v ih (ac) max. 4c. s table is defined as inputs remaining at a hi g h or low level. 4d. floating is defined as inputs at v ref = v dd q/2. 4e. continuous data is defined as half the dq signals changing between hi g h and low every half clock cycle (twice per clock). table 24: i dd operating conditions and maximum limits notes 1?6 on page 48, +0c t c +95c; v dd = max unless otherwise noted description conditions symbol max units -33 -4 -5 s tandby current t ck = idle all banks idle, no inputs toggling i s b 1 (v dd ) x 32 59 59 59 ma i s b 1 (v dd ) x 16 55 55 55 i s b 1 (v ext ) 12 12 12 active standby current t ck = min, c s # = 1 no commands, half address/data toggle up to once every 4 clock cycles i s b 2 (v dd ) x 32 280 271 228 ma i s b 2 (v dd ) x 16 255 244 205 i s b 2 (v ext ) 12 12 12 incremental current bl = 2, t ck = min, t rc = min, 1 bank active, half address data toggles once per t rc, read followed by write sequence i dd 1 (v dd ) x 32 287 266 240 ma i dd 1 (v dd ) x 16 263 243 221 i dd 1 (v ext ) 16 16 16 incremental current bl = 4, t ck = min, t rc = min, 1 bank active, half address/data toggle once per t rc, read followed by write sequence i dd 2 (v dd ) x 32 341 326 300 ma i dd 2 (v dd ) x 16 285 273 250 i dd 2 (v ext ) 20 20 20 burst refresh current t ck = min, t rc = min cyclic bank refresh, data inputs are switching i ref 1 (v dd ) x 32 535 495 405 ma i ref 1 (v dd ) x 16 525 480 402 i ref 1 (v ext ) 79 68 57 distributed refresh current t ck = min, t rc = min s ingle bank refresh, half address/data toggle i ref 2 (v dd ) x 32 282 268 249 ma i ref 2 (v dd ) x 16 265 254 231 i ref 2 (v ext ) 20 20 20 operating supply current example bl = 2, t ck = min, 8 bank cyclic access, half of address bits change every 4 clock cycles, continuous data i dd 2 w (v dd ) x 32 807 706 598 ma i dd 2 w (v dd ) x 16 713 616 519 i dd 2 w (v ext ) 46 40 34 operating supply current example bl = 4, t ck = min, 8 bank cyclic access, half of address bits change every 2 clocks, continuous data i dd 4 w (v dd ) x 32 723 634 521 ma i dd 4 w (v dd ) x 16 549 476 392 i dd 4 w (v ext ) 46 40 34 operating burst read current example bl = 2, cyclic bank access, half of address bits change every clock cycle, measurement is taken during continuous read i dd 2r (v dd ) x32 685 585 490 ma i dd 2r (v dd ) x16 620 525 440 i dd 2r (v ext ) 46 40 34 operating burst read current example bl = 4, cyclic bank access, half of address bits change every two clocks, measurement is taken during continuous read i dd 4r (v dd ) x32 585 530 435 ma i dd 4r (v dd ) x16 550 475 390 i dd 4r (v ext ) 46 40 34
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 38 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram electrical characteristics 4f. continuous address is defined as half the address signals changing between hi g h and low every clock cycle (once per clock). 4g. s equential bank access is de fined as the bank address incrementing by one every t rc. 4h. cyclic bank access is defined as the bank address incrementing by one for each com- mand access. for bl = 2 this is every clock, and for bl = 4 this is every other clock. 5. c s # is hi g h unless a read, write, aref, or mr s command is registered. c s # never transi- tions more than once per clock cycle. 6. i dd parameters are specified with odt disabled.
pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 39 ?2001 micron technology, inc. all rights reserved. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram package dimensions package dimensions figure 31: 144-ball fbga notes: 1. dimensions are in millimeters. s eatin g plane 0.155 0.013 0.75 0.05 0.10 a a ball a1 id ball a1 id ball a1 mold compound: epoxy novolac s ub s trate material: pla s tic laminate 1.20 max s older ball material: 62% s n, 36% pb, 2%ag or 96.5% s n, 3%ag, 0.5%cu 18.50 0.10 17.00 1.00 typ 4.40 11.00 0.10 5.50 0.05 8.50 9.25 0.05 ball a12 144x 0.45 ? dimen s ion s apply to s older ball s po s t reflow. the pre-reflow ball i s ?0.50 on a ?0.40 n s md ball pad. c l c l 8.80 2.20 0.025 ctr 0.80 typ
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo ar e trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified ov er the complete power supply and temperature range for production devices. althou gh considered final, these specifications are subject to change, as further product development and data characte rization sometimes occur. 256mb: x16, x32 2.5v v ext , 1.8v v dd , 1.8v v dd q, rldram package dimensions pdf: 09005aef81121545/source: 09005aef810c0ffc micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16x32rldram_2.fm - rev h 9/06 en 40 ?2001 micron technology, inc. all rights reserved. figure 32: 144-ball bga notes: 1. all dimensions are in millimeters. ball a1 id 17.90 ctr 0.44 0.05 0.39 0.05 ball a1 ball a1 id 0.08 a a s eatin g plane 10o typ 0.08 max 10.70 ctr 11.00 0.10 4.40 5.50 0.05 8.80 2.41 ctr 0.80 typ 1.00 typ 9.25 0.05 8.50 15.40 17.00 18.50 0.10 144x ? 0.45 dimen s ion s apply to s older ball s po s t reflow. the pre-reflow ball diameter i s 0.50 on a 0.40 s md ball pad. ball a12 mold compound: epoxy novolac s ub s trate material: pla s tic laminate s older ball material: 62% s n, 36% pb, 2%ag or 96.5% s n, 3%ag, 0.5% cu

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